Blog
Notes from
the workbench.
On verification, provenance, and the discipline behind AI-native hardware engineering. Specific, technical, occasional.
- 2026.06.11 provenance
Lineage, or it didn't happen
Every artifact in a release package traces to the input that produced it. What that chain looks like, and why integrators should demand one.
Read → - 2026.06.10 verification
A passing testbench proves nothing - until it can fail
Inside the Regex Accelerator UVM campaign: 66 tests, a hard protocol gate, three suspected RTL bugs that were not, and why the zero matters.
Read → - 2026.06.08 fabric
Anatomy of a Fabric run
What actually happens between a product brief and a 39-block verified IP repository - stage by stage, gate by gate.
Read → - 2026.06.02 fpga
Patterns are data, not gates
Why the Regex Accelerator keeps its rules in runtime-programmable tables instead of compiling them into logic - and what that trade actually costs.
Read → - 2026.05.12 verification
Verification is the product
Generated RTL is cheap. The evidence that it is correct is what you are actually buying, and what we actually sell.
Read → - 2026.02.18 benchmarks
A benchmark without conditions is a rumor
Why every number we publish carries its operating conditions, and why standalone performance claims are worse than no claim at all.
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