Vosken Fabric
From one brief to
a verified IP repository.
Vosken Fabric is our AI-native development system, and a flagship product in its own right. It runs a gated pipeline from requirements to release - each stage validated before the next begins, every artifact traceable to the input that produced it.
Each stage gates the next.
Nothing advances until the prior stage is validated. The same discipline that produced the Regex Accelerator runs on every IP we build.
-
Requirements
Capture design intent as numbered, traceable requirements, then review and freeze them.
-
Architecture
Define external interfaces, decompose subsystems, assign protocols, and plan clock, reset, and power.
-
Hierarchy
Break each subsystem into leaf blocks and allocate the register map across them.
-
Micro-architecture
Design ports, registers, data paths, and state machines for every block.
-
RTL
Generate synthesizable, lint-clean SystemVerilog within the frozen architecture.
-
Formal
Prove properties with SVA and SymbiYosys - the appropriate method for each requirement.
-
Coherence
Cross-stage validators confirm every artifact is consistent end to end.
-
Bring-up
Simulate the assembled IP and run regression until it passes.
-
Release
Sign, checksum, and package the proof bundle.
Reuse, not reinvention.
Fabric draws on curated, machine-checked libraries, so every block starts from proven foundations - not a blank file.
Formally verified primitives
Around 90 SystemVerilog cells - FIFOs, arbiters, CDC, stream, NoC, ECC, and AXI infrastructure - hardened with SymbiYosys formal proofs and a shared assertion library.
Protocol library
AXI, AHB, APB, PCIe, CXL, CCIX, TileLink, Wishbone, DDR / LPDDR / HBM, UFS, and more - signal definitions, handshakes, and generated RTL interfaces.
Register design
Register maps allocated across blocks and validated for bitfield conflicts and capacity.
SystemRDL library
SystemRDL 2.0 register generation - one source of truth for the hardware and software views.
45
specialized agents
18
MCP tool servers
150+
deterministic tools
13
pipeline skills
Generated, then debugged into shape.
The Regex Accelerator did not fall out of one clean run. Fabric generated it stage by stage, then engineers debugged failures, fixed bugs, and tuned the architecture until it verified - the loop verification is meant to drive. Every count below is an artifact from the result, traceable end to end.
73
requirements
numbered and traceable
39
blocks
5 subsystems · 33 leaves · 1 top
4
artifacts / block
ports · datapath · FSM · spec
1
gated run
every artifact traceable to it
$ fabric run vosken_regex_nfa
✓ requirements 73 numbered, frozen
✓ architecture 5 subsystems · interfaces · register maps
✓ hierarchy 33 leaf blocks + IP top
✓ micro-arch 39 specs · ports / datapath / FSM
✓ rtl 39 SystemVerilog modules, lint-gated
✓ formal SVA prove + cover sessions per block
✓ coherence 6 cross-stage validators, all green
✓ bring-up L1-L6 in simulation · 61/61 regression
→ release signed, reproducible proof bundle
actual run artifacts - inspect them on /evidence
A verified IP, and the proof bundle behind it.
-
✓
Requirements traceability
every feature maps to a numbered requirement
-
✓
Verification plans
goal, method, and closure criterion per item
-
✓
Formal proof
SVA properties + bounded / unbounded proofs where applicable
-
✓
UVM & simulation evidence
environments, sequences, scoreboards where required
-
✓
Coverage evidence
functional + code coverage with closure report
-
✓
Documentation
architecture, interfaces, integration guide
-
✓
Sign-off package
checksummed, signed, reproducible
Partner on Fabric
Build your IP on the same system.
We take build-to-spec orders through Fabric and share its direction with partners selectively. Tell us what you need built, and how you will verify it.