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FPGA silicon · verified releases

Verified
Semiconductor
IP

Architecture constrains generation.

Verification validates implementation.

Engineers approve release.

01 Requirements

Numbered, traceable, frozen

02 Architecture

Constrains the generation space

03 Generation

RTL within architectural bounds

04 Verification

Lint · formal · coverage · regression

05 Release

Signed, reproducible package

§ 02 Available Today

One credible artifact
outweighs ten planned ones.

Shown below: only what genuinely exists, with every metric stated under its conditions.

FPGA implementation · AWS F2

Regex Accelerator

A hardware regular-expression matching engine for line-rate packet inspection. Delivered with verification collateral and source lineage.

View Technical Details

NFA capacity

256K states

cond runtime-programmable tables, no resynthesis

Rule capacity

8,192 rules

cond with 512 character-class tables

Operation

250 MHz

cond AWS F2 · Virtex UltraScale+ VU47P

Throughput

9.5 Gbps

cond measured, RTL simulation · 7.4 Gbps dense

§ 03 How We Establish Trust

Trust is not asserted.
It ships in the package.

The gated pipeline

  1. 01

    Requirements

    Numbered, traceable, frozen

  2. 02

    Architecture

    Constrains the generation space

  3. 03

    Generation

    RTL within architectural bounds

  4. 04

    Verification

    Lint · formal · coverage · regression

  5. 05

    Release

    Signed, reproducible package

Every release package includes

09 / 09
  • Requirements traceability

    every RTL feature maps to a numbered requirement

  • Architecture specification

    reviewed micro-architecture, frozen before generation

  • Generated RTL

    synthesizable SystemVerilog, lint-clean

  • Verification collateral

    UVM environment, sequences, scoreboards

  • Coverage results

    functional + code coverage with closure report

  • Formal verification results

    SVA properties, bounded + unbounded proofs

  • Benchmark reports

    throughput / area / timing, with stated conditions

  • Source lineage

    every artifact traceable to its generating input

  • Signed release package

    checksummed, signed, reproducible

§ 04 A Real Engineering Workflow

A worked example:
process, not promises.

One completed run through the system. Not a hypothetical future capability, a record of how an artifact moves from a written requirement to a released, validated package.

§ 01

Input

  • AXI4-Stream Verification Component requirements specification
§ 02

Generated

  • Architecture
  • RTL
  • SVA assertions
  • Documentation
§ 03

Validated

  • Lint (Verilator)
  • Formal checks (SymbiYosys)
  • Regression testing
§ 04

Output

  • Released engineering package

// every output above is traceable to the input requirement that produced it.

Built by Vosken Fabric

One brief in.
A verified IP repository out.

The Regex Accelerator was not hand-assembled. It is the output of a single gated run of Vosken Fabric - requirements, architecture, micro-architecture, RTL, and formal collateral generated stage by stage, each stage validated before the next began, every artifact traceable to the stage that produced it.

73

requirements

numbered and traceable

39

blocks

5 subsystems · 33 leaves · 1 top

4

artifacts / block

ports · datapath · FSM · spec

1

gated run

every artifact traceable to it

fabric · run 2026-05-24 complete

$ fabric run vosken_regex_nfa

requirements 73 numbered, frozen

architecture 5 subsystems · interfaces · register maps

hierarchy 33 leaf blocks + IP top

micro-arch 39 specs · ports / datapath / FSM

rtl 39 SystemVerilog modules, lint-gated

formal SVA prove + cover sessions per block

coherence 6 cross-stage validators, all green

bring-up L1-L6 in simulation · 61/61 regression

release signed, reproducible package

actual run artifacts - inspect them on /evidence

§ 05 Industry Engagement
  • Under evaluation by networking & security customers.

  • Commercial engagements in progress.

  • Design-partner conversations active.

// category-level where disclosure is restricted, named references available under NDA.

§ 06 Why This Approach Exists

Semiconductor complexity
is increasing.

  • 01

    Verification debt

    Verification effort is growing faster than design effort.

  • 02

    System complexity

    More interfaces, more state, more ways to be subtly wrong.

  • 03

    Schedule pressure

    Tape-out windows shrink while scope expands.

  • 04

    Capacity limits

    Skilled engineering capacity does not scale linearly.

VoskenAI's response

Combine architectural discipline, automation, verification, and engineering review into a single repeatable development system. The emphasis is engineering discipline, not AI.

emphasis discipline automation verification review

// the emphasis is engineering, not AI.

§ 08 Vision

Traditional engineering organizations scale through headcount. We are exploring a different model: engineering systems that let small teams deliver the output of much larger ones.

You have already seen the evidence. No manifesto is required here.

§ 09 Company

Small Team.
Deliberate Design.

VoskenAI intentionally focuses on building engineering systems rather than large engineering organizations.

Leverage comes from process, automation, verification, and engineering judgment working together. The size of the team is not hidden. It is part of the story.

More about the company