Verification is the product

There is a comfortable story about AI and hardware design that goes like this: describe what you want, and a model writes the RTL. The story is half true, and the true half is the boring half.

Generating plausible SystemVerilog is no longer the hard part. The hard part is the same as it has always been: knowing whether the thing is correct, under which conditions, and being able to prove it to someone who was not in the room when it was written.

Generation without verification is a faster way to ship bugs

Automation amplifies whatever process it sits on top of. If your process produces unverified RTL, automation produces unverified RTL faster. That is not progress; it is a larger blast radius.

This is why we treat verification as the deliverable, not a checkbox at the end:

• Every feature in the RTL maps back to a numbered requirement.
• Architecture is frozen before generation, so generation has bounds.
• Lint, formal, coverage, and regression each close before a release exists.

The RTL is the part everyone looks at. The verification collateral is the part that should change your mind.

What “evidence” means here

When we say a block is done, we mean there is a package you can open: the requirements, the architecture it was generated against, the properties that were proven, the coverage that was closed, the benchmarks with their conditions, and a signed manifest tying it all together.

Concretely: the Regex Accelerator repository contains 39 blocks, and verification is organised per block - each one carries its own SVA properties with separate prove and cover sessions, its own lint record, its own review findings. “The design passed” is not a sentence we can even express; the unit of evidence is the block, and the release is the sum of blocks whose evidence closed.

You should not have to trust us. You should be able to check.

That is the whole idea. Architecture constrains generation. Verification validates implementation. Engineers approve release.